Data block switching at a memory sub-system

ABSTRACT

Incoming host data is programmed to a first set of data blocks indicated by a first cursor of a memory sub-system. The first set of blocks is associated with a first write mode. A determination is made that a second set of blocks associated with a second write mode is available to store the incoming host data prior to closing one or more of the first set of blocks. The incoming host data is programmed to the second set of blocks in view of a second cursor of the memory sub-system. A media management operation is performed to close the one or more of the first set of blocks.

RELATED APPLICATION

The present Application is a Continuation of U.S. patent applicationSer. No. 16/725,792, filed on Dec. 23, 2019, entitled “DATA BLOCKSWITCHING AT A MEMORY SUB-SYSTEM,” which is incorporated herein byreference in its entirety for all purposes.

TECHNICAL FIELD

The present disclosure generally relates to a memory sub-system, andmore specifically, relates to data block switching at a memorysub-system.

BACKGROUND

A memory sub-system can include one or more memory devices that storedata. The memory devices can be, for example, non-volatile memorydevices and volatile memory devices. In general, a host system canutilize a memory sub-system to store data at the memory devices and toretrieve data from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousimplementations of the disclosure.

FIG. 1 illustrates an example computing system that includes a memorysub-system in accordance with embodiments of the present disclosure.

FIG. 2 illustrates a flow diagram of an example method to perform datablock switching for writing host data at an example memory device, inaccordance with some embodiments of the present disclosure.

FIG. 3A illustrates an example memory device associated with a firstwrite mode and a second write mode, in accordance with some embodimentsof the present disclosure.

FIG. 3B illustrates switching from writing host data to a first openblock associated with a first write mode to a second available datablock associated with a second write mode of an example memory device,in accordance with some embodiments of the present disclosure.

FIG. 3C illustrates writing host data to a second available data blockin the second write mode of an example memory device, in accordance withsome embodiments of the present disclosure.

FIG. 4 illustrates a flow diagram of an example method to perform datablock switching for garbage collection, in accordance with someembodiments of the present disclosure.

FIG. 5A illustrates an example memory device for performing a garbagecollection operation, in accordance with some embodiments of the presentdisclosure.

FIG. 5B illustrates performing data block switching for a garbagecollection operation for an example memory device, in accordance withsome embodiments of the present disclosure.

FIG. 5C illustrates performing a garbage collection operation for anexample memory device, in accordance with some embodiments of thepresent disclosure.

FIG. 6 is a block diagram of an example computer system in whichimplementations of the present disclosure can operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to data block switchingat a memory sub-system. A memory sub-system can be a storage device, amemory module, or a hybrid of a storage device and memory module.Examples of storage devices and memory modules are described below inconjunction with FIG. 1. In general, a host system can utilize a memorysub-system that includes one or more components, such as memory devicesthat store data. The host system can provide data to be stored at thememory sub-system and can request data to be retrieved from the memorysub-system.

A memory device can be a non-volatile memory device. A non-volatilememory device is a package of one or more dice. Each die can consist ofone or more planes. Planes can be groups into logic units (LUNs). Forsome types of non-volatile memory devices (e.g., NAND devices), eachplane consists of a set of physical blocks. Each block consists of a setof pages. Each page consists of a set of memory cells (“cells”). A cellis an electronic circuit that stores information. A data blockhereinafter refers to a unit of the memory device used to store data andcan include a group of memory cells, a word line group, a word line, orindividual memory cells.

Data operations can be performed by the memory sub-system. The dataoperations can be host-initiated operations. For example, the hostsystem can initiate a data operation (e.g., write, read, erase, etc.) ona memory sub-system. The host system can send access requests (e.g.,write command, read command) to the memory sub-system, such as to storedata on a memory device at the memory sub-system and to read data fromthe memory device on the memory sub-system. The data to be read orwritten, as specified by a host request, is hereinafter referred to as“host data.” A host request can include logical address information(e.g., logical block address (LBA), namespace) for the host data, whichis the location the host system associates with the host data. Thelogical address information (e.g., LBA, namespace) can be part ofmetadata for the host data. Metadata can also include error handlingdata (e.g., ECC code word, parity code), data version (e.g. used todistinguish age of data written), valid bitmap (which LBAs or logicaltransfer units contain valid data), etc.

A memory sub-system can perform various operations with respect to oneor more memory devices included in the memory sub-system. For example,read operations, program (i.e., write) operations, and erase operationscan be performed at one or more memory devices. Memory devices caninclude one or more data blocks, which can include one or more arrays ofmemory cells such as single level cells (SLCs) that are each used tostore a single bit of data or memory cells that each store multiple bitsof data, such as multi-level cells (MLCs), triple-level cells (TLCs), orquad-level cells (QLCs) (collectively referred to herein as XLCs). Eachmemory cell type can have a different data density, which corresponds toan amount of data (e.g., bits of data) that can be stored per memorycell.

A memory device can be configured to include one or more data blockswith SLCs (referred to as SLC data blocks) and one or more data blockswith XLCs (referred to as XLC data blocks). The memory device can alsobe configured such that a first portion of the memory device isprovisioned as a cache while a second portion of the memory device isprovisioned as a user space. In some conventional memory sub-systems,the cache can include one or more SLC memory units (e.g., blocks) andthe user space can include one or more XLC memory units. A memory unitcan include a group of memory cells, a word line group, a word line, orindividual memory cells. For example, a memory unit can include one ormore blocks. The cache can also be provisioned to include one or moreXLC memory units so that the cache includes both SLC memory units andXLC memory units. In response to a determination that additional userspace is to be provisioned at the memory device, the XLC memory units ofthe cache can be re-configured as user space memory units.

A host cursor can be used to manage the performance of the writeoperation. A cursor can manage the execution of a memory operation bydetermining where, when, and in what sequence to write host data tomemory devices. In some examples, a cursor can be a pointer to anavailable data block of the memory device. The host cursor can indicatean available data block (also referred to as an open block or an opendata block) of the memory device that is available to store incominghost data. In some examples, the available data block can be an emptydata block where all memory cells of the data block are available tostore host data, or a partially empty data block where data is writtento one or more memory cells of the data block while one or more othermemory cells of the data block are available to store host data. Inconventional memory sub-systems, a single host cursor can be used tomanage the performance of write operations. The cache can include one ormore available data blocks and the host cursor can indicate an availabledata block of the cache to store incoming host data, in SLC mode or inXLC mode. In response to determining that the cache does not include anavailable data block, the host cursor can indicate an available datablock of the user space to store incoming host data in XLC mode.Subsequent incoming host data can be written to available user spacedata blocks, as indicated by the host cursor, until the user space doesnot include an available data block.

During operation of the memory sub-system, an idle time period can occurwhere incoming host data is not received to be stored at the memorysub-system. In some instances, no cache data blocks are available forincoming host data and one or more user space data blocks are availablefor incoming host data at the initiation of the idle time period. Assuch, at the initiation of the idle time period, the host cursor canindicate a user space data block as an available data block. Theavailable user space data block indicated by the host cursor can be apartially empty data block. A media management operation, such as agarbage collection operation, can be performed at the memory sub-systemduring the idle time period to make one or more data blocks of the cacheand/or the user space available for subsequent incoming host data. Afterthe idle time period is complete, incoming host data can be received tobe stored at the memory sub-system. In response to the host cursor, atthe initiation of the idle time period, indicating a partially availabledata block as an available user data block, incoming host data can bestored at the partially available data block in XLC mode instead of anewly available cache data block in SLC mode.

Conventional memory sub-systems do not provide a mechanism for host datato be written to available cache data blocks in SLC mode if a user spacedata block is not closed (i.e., is available). As a result, incominghost data is written to the available user space data block in XLC modeto close the available user space data block even though one or morecache data blocks are available. A data block can be considered to beclosed when data is written to each memory cell of the data block. Asignificant reduction in write performance results since instead ofwriting host data to the available cache data block in SLC mode, hostdata is written to the available user space data block in XLC mode toclose the user space data block, and the XLC mode latency is larger thanthe SLC mode latency.

Aspects of the present disclosure address the above and otherdeficiencies by providing a first available data block, indicated by afirst host cursor, and a second available data block, indicated by asecond host cursor. By providing a second host cursor to indicate thesecond available data block, a mechanism is provided for host data to bewritten to the cache in SLC mode even though a user space data block,opened in XLC mode, is not closed. The first host cursor and the secondhost cursor can serve as a record of available data blocks in both thecache and the user space of the memory sub-system. Using the first hostcursor and the second host cursor, the memory sub-system can identifyand select an available data block to write incoming host data to reducewrite operation latency.

Advantages of the present disclosure include, but are not limited to, animproved performance of the memory sub-system as the overall writeoperation latency can be reduced. For example, host data can be writtento a cache data block in SLC mode rather than a user space data block inXLC mode, even though the user space data block has not been closed(i.e., contains one or more available XLCs). Thus, by providing at leasta second host cursor to indicate a second available data block, a writeoperation can be successfully performed in less time than if only oneavailable data block was indicated by a first host cursor. As such,since the write operation can be performed in less time, the overallwrite latency of the memory sub-system can be decreased. The decreasingof the write latency can result in the memory sub-system being capableof satisfying Quality of Service (QoS) requirements that specify variousoperating requirements when performing the write operations at thememory sub-system.

FIG. 1 illustrates an example computing system 100 that includes amemory sub-system 110 in accordance with some embodiments of the presentdisclosure. The memory sub-system 110 can include media, such as one ormore volatile memory devices (e.g., memory device 140), one or morenon-volatile memory devices (e.g., memory device 130), or a combinationof such.

A memory sub-system 110 can be a storage device, a memory module, or ahybrid of a storage device and memory module. Examples of a storagedevice include a solid-state drive (SSD), a flash drive, a universalserial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC)drive, a Universal Flash Storage (UFS) drive, a secure digital (SD)card, and a hard disk drive (HDD). Examples of memory modules include adual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), andvarious types of non-volatile dual in-line memory module (NVDIMM).

The computing system 100 can be a computing device such as a desktopcomputer, laptop computer, network server, mobile device, a vehicle(e.g., airplane, drone, train, automobile, or other conveyance),Internet of Things (IoT) enabled device, embedded computer (e.g., oneincluded in a vehicle, industrial equipment, or a networked commercialdevice), or such computing device that includes memory and a processingdevice.

The computing system 100 can include a host system 120 that is coupledto one or more memory sub-systems 110. In some embodiments, the hostsystem 120 is coupled to different types of memory sub-system 110. FIG.1 illustrates one example of a host system 120 coupled to one memorysub-system 110. As used herein, “coupled to” or “coupled with” generallyrefers to a connection between devices, which can be an indirectcommunicative connection or direct communicative connection (e.g.,without intervening devices), whether wired or wireless, includingconnections such as electrical, optical, magnetic, etc.

The host system 120 can include a processor chipset and a software stackexecuted by the processor chipset. The processor chipset can include oneor more cores, one or more caches, a memory controller (e.g., NVDIMMcontroller), and a storage protocol controller (e.g., PCIe controller,SATA controller). The host system 120 uses the memory sub-system 110,for example, to write data to the memory sub-system 110 and read datafrom the memory sub-system 110.

The host system 120 can be coupled to the memory sub-system 110 via aphysical host interface. Examples of a physical host interface include,but are not limited to, a serial advanced technology attachment (SATA)interface, a peripheral component interconnect express (PCIe) interface,universal serial bus (USB) interface, Fibre Channel, Serial AttachedSCSI (SAS), a double data rate (DDR) memory bus, Small Computer SystemInterface (SCSI), a dual in-line memory module (DIMM) interface (e.g.,DIMM socket interface that supports Double Data Rate (DDR)), Open NANDFlash Interface (ONFI), Double Data Rate (DDR), Low Power Double DataRate (LPDDR), or any other interface. The physical host interface can beused to transmit data between the host system 120 and the memorysub-system 110. The host system 120 can further utilize an NVM Express(NVMe) interface to access components (e.g., memory devices 130) whenthe memory sub-system 110 is coupled with the host system 120 by thePCIe interface. The physical host interface can provide an interface forpassing control, address, data, and other signals between the memorysub-system 110 and the host system 120. FIG. 1 illustrates a memorysub-system 110 as an example. In general, the host system 120 can accessmultiple memory sub-systems via a same communication connection,multiple separate communication connections, and/or a combination ofcommunication connections.

The memory devices 130,140 can include any combination of the differenttypes of non-volatile memory devices and/or volatile memory devices. Thevolatile memory devices (e.g., memory device 140) can be, but are notlimited to, random access memory (RAM), such as dynamic random accessmemory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device 130)include negative-and (NAND) type flash memory and write-in-place memory,such as a three-dimensional cross-point (“3D cross-point”) memorydevice, which is a cross-point array of non-volatile memory cells. Across-point array of non-volatile memory can perform bit storage basedon a change of bulk resistance, in conjunction with a stackablecross-gridded data access array. Additionally, in contrast to manyflash-based memories, cross-point non-volatile memory can perform awrite in-place operation, where a non-volatile memory cell can beprogrammed without the non-volatile memory cell being previously erased.NAND type flash memory includes, for example, two-dimensional NAND (2DNAND) and three-dimensional NAND (3D NAND).

Each of the memory devices 130 can include one or more arrays of memorycells. One type of memory cell, for example, single level cells (SLC)can store one bit per cell. Other types of memory cells, such asmulti-level cells (MLCs), triple level cells (TLCs), and quad-levelcells (QLCs), can store multiple bits per cell. In some embodiments,each of the memory devices 130 can include one or more arrays of memorycells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. Insome embodiments, a particular memory device can include an SLC portion,and an MLC portion, a TLC portion, or a QLC portion of memory cells. Thememory cells of the memory devices 130 can be grouped as pages that canrefer to a logical unit of the memory device used to store data. Withsome types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory devices such as 3D cross-point array ofnon-volatile memory cells and NAND type flash memory (e.g., 2D NAND, 3DNAND) are described, the memory device 130 can be based on any othertype of non-volatile memory, such as read-only memory (ROM), phasechange memory (PCM), self-selecting memory, other chalcogenide basedmemories, ferroelectric transistor random-access memory (FeTRAM),ferroelectric random access memory (FeRAM), magneto random access memory(MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM(CBRAM), resistive random access memory (RRAM), oxide based RRAM(OxRAM), negative-or (NOR) flash memory, and electrically erasableprogrammable read-only memory (EEPROM).

A memory sub-system controller 115 (or controller 115 for simplicity)can communicate with the memory devices 130 to perform operations suchas reading data, writing data, or erasing data at the memory devices 130and other such operations. The memory sub-system controller 115 caninclude hardware such as one or more integrated circuits and/or discretecomponents, a buffer memory, or a combination thereof. The hardware caninclude a digital circuitry with dedicated (i.e., hard-coded) logic toperform the operations described herein. The memory sub-systemcontroller 115 can be a microcontroller, special purpose logic circuitry(e.g., a field programmable gate array (FPGA), an application specificintegrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller 115 can include a processor 117 (e.g.,processing device) configured to execute instructions stored in localmemory 119. In the illustrated example, the local memory 119 of thememory sub-system controller 115 includes an embedded memory configuredto store instructions for performing various processes, operations,logic flows, and routines that control operation of the memorysub-system 110, including handling communications between the memorysub-system 110 and the host system 120.

In some embodiments, the local memory 119 can include memory registersstoring memory pointers, fetched data, etc. The local memory 119 canalso include read-only memory (ROM) for storing micro-code. While theexample memory sub-system 110 in FIG. 1 has been illustrated asincluding the memory sub-system controller 115, in another embodiment ofthe present disclosure, a memory sub-system 110 does not include amemory sub-system controller 115, and can instead rely upon externalcontrol (e.g., provided by an external host, or by a processor orcontroller separate from the memory sub-system).

In general, the memory sub-system controller 115 can receive commands oroperations from the host system 120 and can convert the commands oroperations into instructions or appropriate commands to achieve thedesired access to the memory devices 130. The memory sub-systemcontroller 115 can be responsible for other operations such as wearleveling operations, garbage collection operations, error detection anderror-correcting code (ECC) operations, encryption operations, cachingoperations, and address translations between a logical address (e.g.,logical block address (LBA), namespace) and a physical address (e.g.,physical block address) that are associated with the memory devices 130.The memory sub-system controller 115 can further include host interfacecircuitry to communicate with the host system 120 via the physical hostinterface. The host interface circuitry can convert the commandsreceived from the host system into command instructions to access thememory devices 130 as well as convert responses associated with thememory devices 130 into information for the host system 120.

The memory sub-system 110 can also include additional circuitry orcomponents that are not illustrated. In some embodiments, the memorysub-system 110 can include a cache or buffer (e.g., DRAM) and addresscircuitry (e.g., a row decoder and a column decoder) that can receive anaddress from the memory sub-system controller 115 and decode the addressto access the memory devices 130.

In some embodiments, the memory devices 130 include local mediacontrollers 135 that operate in conjunction with memory sub-systemcontroller 115 to execute operations on one or more memory cells of thememory devices 130. An external controller (e.g., memory sub-systemcontroller 115) can externally manage the memory device 130 (e.g.,perform media management operations on the memory device 130). In someembodiments, a memory device 130 is a managed memory device, which is araw memory device combined with a local controller (e.g., localcontroller 135) for media management within the same memory devicepackage. An example of a managed memory device is a managed NAND (MNAND)device.

The memory subsystem 110 includes a cursor component 113 that can beused to maintain two or more host cursors of the memory sub-system 110.In some embodiments, the controller 115 includes at least a portion ofthe cursor component 113. For example, the controller 115 can include aprocessor 117 (processing device) configured to execute instructionsstored in local memory 119 for performing operations described herein.In some embodiments, the cursor component 113 is part of the host system120, an application, or an operating system.

The cursor component 113 can maintain two or more host cursors that eachindicate an available data block of the memory subsystem for host datato be written to. A first host cursor can identify an available datablock of a first portion of the memory sub-system, where the firstportion corresponds to a first write mode. A second host cursor canidentify an available data block of a second portion of the memorysub-system, where the second portion corresponds to a second write mode.The first write mode can correspond to a first number of bits per memorycell of the memory subsystem, and the second write mode can correspondto a second number of bits per memory cell of the memory subsystem. Insome implementations, the first number of bits per memory cell is largerthan the second number of bits per memory cell. In otherimplementations, the second number of bits is larger than the firstnumber of bits. Based on an availability of a data block of the firstportion of the memory sub-system, the cursor component can determine towrite host data at the data block associated with the first host cursoror a data block associated with the second host cursor. Further detailswith regards to the operations of the cursor component 113 are describedherein.

FIG. 2 is a flow diagram of an example method 200 to perform data blockswitching for writing host data at an example memory device, inaccordance with some embodiments of the present disclosure. The method200 can be performed by processing logic that can include hardware(e.g., processing device, circuitry, dedicated logic, programmablelogic, microcode, hardware of a device, integrated circuit, etc.),software (e.g., instructions run or executed on a processing device), ora combination thereof. In some embodiments, the method 200 is performedby the cursor component 113 of FIG. 1. Although shown in a particularsequence or order, unless otherwise specified, the order of theprocesses can be modified. Thus, the illustrated embodiments should beunderstood only as examples, and the illustrated processes can beperformed in a different order, and some processes can be performed inparallel. Additionally, one or more processes can be omitted in variousembodiments. Thus, not all processes are required in every embodiments.Other process flows are possible.

At operation 210, the processing device receives host data to be writtento a memory sub-system. The memory sub-system can include one or morememory devices, where each memory device can include one or more datablocks. Each data block can include one or more arrays of memory cells,such SLCs or XLCs. Each memory cell type can have a different datadensity, which corresponds to an amount of data (e.g., bits of data)that can be stored per memory cell.

The memory sub-system can be configured such that one or more portionsof the memory sub-system are used in various modes. For example, a firstportion of the memory sub-system can be used as a cache and secondportion of the memory sub-system can be exposed as user space. The cachecan be a portion of the memory sub-system where host data is temporarilystored prior to being moved for long-term storage at the user space. Insome embodiments, data written to one or more blocks of the cache can bewritten in SLC mode. In other or similar embodiments, data written toone or more blocks of user space can be written in XLC mode. If no cacheblocks are available to store incoming host data in SLC mode, host datacan be written to user space in XLC mode, rather than data being firstwritten at the cache in SLC mode and then rewritten at the user space inXLC mode.

At operation 220, the processing device writes a first portion of thehost data to a first available data block of the memory sub-system,where the first available data block is associated with a first writemode. The first available data block can be an empty data block (i.e.,all memory cells of the data block are available for host data) or apartially empty data block (i.e., data is written to one or more memorycells of the data block and one or more other memory cells of the datablock are available for host data). In some examples, the firstavailable data block can be included in the first portion of the memorysub-system (i.e., the user space), where the first portion correspondsto at least the first write mode. The first write mode can correspond toprogramming the first number of bits per memory cell of the firstavailable data block. For example, the first available data block caninclude one or more QLCs. As a result, the first write mode can be a QLCwrite mode. The first open block can be identified as an available datablock by a first host cursor.

At operation 230, the processing device receives an indication that asecond available data block of the memory sub-system is available forhost data, where the second available data block is associated with asecond write mode. In some examples, the second available data block canbe included in the second portion of the memory sub-system (i.e., thecache), where the second portion corresponds to at least the secondwrite mode. The second write mode can correspond to a second number ofbits per memory cell of the second available data block. For example,the second available data block can include one or more SLCs. As aresult, the second write mode can be an SLC write mode. The secondavailable data block can be identified as an available data block by asecond host cursor.

The indication that a second available data block is available can betransmitted to the processing device as a result of a garbage collectionoperation being completed on one or more data blocks of the secondportion of the memory sub-system.

At operation 240, the processing device determines to write a secondportion of the host data to the second available data block based on thereceived indication. In some examples, when the indication is received,the first available data block can be available for the second portionof the host data (i.e., can contain one or more XLCs). The processingdevice can determine to write the second portion of the host data to thesecond available data block before the first available data block isclosed. For example, data can be written to the second available datablock before data is written to all memory cells of the first availabledata. The processing device can determine to write the second portion ofthe host data to the second available data block because the secondavailable data block is associated with a smaller number of bits permemory cell than the first available data block and, as a result, awrite operation latency associated with writing the second portion ofthe host data to the second available data block is less than a writeoperation latency associated with writing the second portion of the hostdata to the first available data block.

At operation 250, the processing device, in response to determining towrite the second portion of the host data to the second available datablock, writes the second portion of the host data to the secondavailable data block in the second write mode prior to closing the firstopen block in the first write mode. For example, the second portion ofthe host data can be written to the second available data block prior tohost data being written to each memory cell of the first open block.

FIG. 3A illustrates an example memory device 300, in accordance withsome embodiments of the present disclosure. In some embodiments, thememory device 300 can include a first portion 310 and a second portion320. The first portion 310 and the second portion 320 can be portions ofa single memory device 300. In other embodiments, the first portion 310can be a first memory device and the second portion 320 can be a secondmemory device of the memory sub-system.

The first portion 310 and the second portion 320 can each include atleast one data block. Each data block can include one or more arrays ofmemory cells, such as SLCs or XLCs. In some embodiments, a data blockcan be at least one of a closed data block 330 or an available datablock (i.e., empty data block 340 or partially empty data block 350). Aclosed data block 330 can be a data block where all memory cells arefilled with at least one of host data or garbage collection data. Thehost data can be data received from a host system (e.g., host system 120of FIG. 1) to be written to memory device 300. The garbage collectiondata can include data that previously was written to a data block ofmemory device 300 and has been moved to another data block during agarbage collection process. The closed data block 330 can be completelyfilled with data, and therefore is not available for data to be writtento. As discussed previously, an available data block can include atleast one memory cell that is available to store new host data.

The one or more data blocks of the first portion 310 can be associatedwith a first write mode. The first write mode can correspond to a firstnumber of bits per memory cell of each data block. In some embodiments,the first write mode can correspond to two or more bits per memory cell(i.e., XLCs). The one or more data blocks of the second portion 320 canbe associated with a second write mode. The second write mode cancorrespond to a second number of bits per memory cell of each datablock. In some embodiments, the second write mode can correspond to onebit per memory cell (i.e., SLCs). In some embodiments, the first numberof bits per memory cell of the first write mode can be larger than thesecond number of bits per memory cell of the second write mode.

The first portion 310 can correspond to a first host cursor 360, andsecond portion 320 can correspond to a second host cursor 370. The firsthost cursor 360 can indicate a data block of the first portion 310 thatis available to write incoming host data, while the second host cursor370 can indicate a data block of the second portion 320 that isavailable to write incoming host data.

FIG. 3B illustrates switching from writing host data to a firstavailable data block 380 associated with a first write mode to a secondavailable data block 390 associated with a second write mode of anexample memory device 300, in accordance with some embodiments of thepresent disclosure. Host data can be received by memory device 300 froma host system, where the host data is to be written to a first availabledata block 380 of memory device 300. As host data is written to thefirst available data block 380, the memory cells of the first availabledata block 380 can be filled with host data, such that the firstavailable data block 380 becomes closed. If the first available datablock 380 becomes closed, the first host cursor 360 can be updated toindicate another available data block of the first write mode portionfor which to write host data.

An indication can be received that a second available data block 390 ofmemory device 300 is available for storing host data. In someembodiments, the second available data block 390 can be an availabledata block of the second portion 320. Based on the received indication,the processing device can determine whether to write a second portion ofthe host data to the first available data block 380 of memory device300, indicated by the first host cursor 360, or the second availabledata block 390 of memory device 300, indicated by the second host cursor370. In some examples, the first available data block 380 indicated bythe first host cursor 360 can be a partially empty data block. Insteadof writing the second portion of the host data to the partially emptyfirst available data block 380, the processing device can determine towrite the second portion of the host data to the second available datablock 390 before closing the first available data block 380. Theprocessing device can determine to write the second portion of the hostdata to the second available data block 390 because the second availabledata block 390 is associated with a smaller number of bits per memorycell than the first available data block 380 and, as a result, a writeoperation latency associated with writing the second portion of the hostdata to the second available data block 390 is less than a writeoperation latency associated with writing the second portion of hostdata to the first available data block 380.

FIG. 3C illustrates writing host data to the second available data block390 in a second write mode of an example memory device 300, inaccordance with some embodiments of the present disclosure. Theprocessing device can determine to write a second portion of host datato the second available data block 390 in the second write mode.

Responsive to determining to write the second portion of host data tothe second available data block 390, the second portion of host data canbe written to the second available data block 390. The second availabledata block 390 can be indicated by the second host cursor 370. As hostdata is written to the second available data block 390, the memory cellsof the second available data block 390 can be filled with host data,such that the second available data block 390 becomes closed. If thesecond available data block 390 becomes closed, the second host cursor370 can be updated to indicate another available data block of thesecond portion 320 for which to write host data. Host data can bewritten to available data blocks of the second portion 320 until alldata blocks of the second portion 320 are closed, or no incoming hostdata is received.

FIG. 4 is a flow diagram of an example method 400 to perform data blockswitching for garbage collection, in accordance with some embodiments ofthe present disclosure. The method 400 can be performed by processinglogic that can include hardware (e.g., processing device, circuitry,dedicated logic, programmable logic, microcode, hardware of a device,integrated circuit, etc.), software (e.g., instructions run or executedon a processing device), or a combination thereof. In some embodiments,the method 400 is performed by the cursor component 113 of FIG. 1.Although shown in a particular sequence or order, unless otherwisespecified, the order of the processes can be modified. Thus, theillustrated embodiments should be understood only as examples, and theillustrated processes can be performed in a different order, and someprocesses can be performed in parallel. Additionally, one or moreprocesses can be omitted in various embodiments. Thus, not all processesare required in every embodiment. Other process flows are possible.

At operation 410, the processing device receives an indication toperform a garbage collection operation for a data block of a memorydevice. The memory device can include one or more data blocks, whereeach data block includes one or more arrays of memory cells, such asSLCs or XLCs. In some examples, the memory device can be configured suchthat one or more portions are reserved for various purposes. A firstportion of the memory device can be provisioned as a cache, where one ormore cache data blocks are configured to be written in SLC mode. Asecond portion of the memory device can be configured as user space,where one or more user space data blocks are configured to be written inXLC mode.

The garbage collection operation can include identifying data blocks inthe first portion of the memory device that contain unneeded data andclear the data blocks to maintain optimal write speeds. The garbagecollection operation can further include writing needed data to a datablock of the second portion of the memory device and removing thewritten data from the first portion.

At operation 420, the processing device identifies a first availabledata block of the memory device that corresponds to a host cursor and asecond available data block of the memory device that corresponds to agarbage collection cursor. The host cursor can indicate an availabledata block of the memory device that contains memory cells that areavailable for host data to be written to. The garbage collection cursorcan indicate an available data block of the memory device that isreserved for storing garbage collection data (i.e., data that has beenwritten and removed from a block previously subject to a garbagecollection operation).

At operation 430, the processing device determines whether to write dataof the data block subject to the garbage collection operation to thefirst available data block or the second available data block based on acondition of the first available data block. In some examples, thecondition of the first available data block can be whether the firstavailable data block is a partially empty data block. The processingdevice can determine to write data from the data block subject to thegarbage collection operation to the partially empty first available datablock to close the first available data block, rather than writing dataof the data block to the second available data block.

At operation 440, in response to determining to write the data of thedata block to the first available data block, the processing devicestores data of the data block to the first available data block to closethe first available data block. The processing device can determine towrite the data to the first available data block based on a memorypolicy in favor of closing a partially empty block before writing to adifferent available data block. Once the first available data block isclosed, data can no longer be written to the first available data block,as all memory cells of the first available data block are filled. Theprocessing device can determine to write data from other data blockssubject to the garbage collection operation to the second available datablock of the memory device that corresponds to the garbage collectioncursor.

FIG. 5A illustrates an example memory device 500 for performing agarbage collection operation, in accordance with some embodiments of thepresent disclosure. In some embodiments, the memory device 500 caninclude a first portion 510 and a second portion 520. The first portion510 and the second portion 520 can be portions of a single memory device500. In other embodiments, the first portion 510 can be a first memorydevice and the second portion 520 can be a second memory device.

The first portion 510 and the second portion 520 can each include atleast one data block. Each data block can include one or more arrays ofmemory cells including at least one of SLCs or XLCs. One or more datablocks of the first portion 510 can be associated with a first writemode. The first write mode can correspond to a first number of bits permemory cell of each data block. In some embodiments, the first writemode can correspond to one or more bits per memory cell (i.e., SLCs).One or more data blocks of the second portion 520 can be associated witha second write mode. In some embodiments, the second write mode cancorrespond to a second number of bits per memory cell of each datablock.

The first portion 510 and the second portion 520 can correspond to ahost cursor 530. The host cursor 530 can indicate an available datablock of the first portion 510 or the second portion 520 for whichincoming host data is to be stored. The first portion 510 and the secondportion 520 may further correspond with a garbage collection cursor 570.The garbage collection cursor 570 can indicate an available data blockof the memory device 500 that is reserved for storing garbage collectiondata.

A request can be received to perform a garbage collection operation on adata block of memory device 500. A first data block 580 can be selectedfor garbage collection. First data block 580 can include a closed datablock of first portion 510 and/or second portion 520. In some examples,the first data block 580 can be selected based on an amount of unneededhost data (i.e., invalid data) of the first data block 580. The firstdata block 580 can be selected for garbage collection to remove unneededdata from the first data block 580 to allow for subsequent host data tobe stored.

Responsive to receiving a request to perform the garbage collectionoperation and selecting the first data block 580, a first garbagecollection block and a second garbage collection block can beidentified. The first garbage collection block can be second data block560 indicated by the host cursor 530, and the second garbage collectionblock can be any available data block indicated by the garbagecollection cursor 570. It can be determined whether to write the garbagecollection data of the first data block 580 to the available data block560 or the available data block indicated by the garbage collectioncursor 570 based on a condition of the available data block 560. In someexamples, the condition of the available data block 560 can be whetherthe available data block 560 is a partially empty data block. Theprocessing device can determine to write garbage collection data of thefirst data block 580 to the partially empty second available data block560 to close the second data block 560, rather than writing the garbagecollection data of the first data block 580 to the data block indicatedby the garbage collection cursor 570.

FIG. 5B illustrates performing a garbage collection operation for anexample memory device, in accordance with some embodiments of thepresent disclosure. As discussed above, the processing device candetermine to write garbage collection data of the first data block 580to the partially empty second data block 560 to close the second datablock 560, rather than writing the garbage collection data to theavailable block indicated by the garbage collection cursor 570.Responsive to determining to write the garbage collection data to thesecond data block 560, the garbage collection data of the first datablock 580 (i.e., the needed data), can be written to the second datablock 560 such to fill the second data block 560. The unneeded, andneeded, data written to the first data block 580 can be removed from thefirst data block 580. Responsive to closing the second data block 560,the host cursor 530 can be updated to indicate another available datablock of the second portion 520 of the memory device 500.

FIG. 5C illustrates performing a garbage collection operation for anexample memory device, in accordance with some embodiments of thepresent disclosure. In some examples, a third data block 590 can beselected for garbage collection. An available data block indicated bythe host cursor 530, and an available data block indicated by thegarbage collection cursor 570, can be identified as candidate datablocks to store the garbage collection data of the third data block 590.The processing device can determine whether to write the garbagecollection data of the third data block 590 to the available data blockindicated by the host cursor 530 or the garbage collection cursor 570based on a condition of the available data block indicated by the hostcursor 530. In some examples, the condition can be whether the availabledata block indicated by the host cursor 530 is a partially empty blockResponsive to determining that the available data block indicated by thehost cursor 530 is not a partially empty block (i.e., is an emptyblock), the processing device can determine to write the garbagecollection data of the third data block 590 to the available data blockindicated by the garbage collection cursor 570. In other or similarexamples, the condition can further be whether the host cursor 530indicates a block in the second portion 520. Responsive to furtherdetermining that the host cursor 530 does not indicate a block in thesecond portion 520, (i.e., indicates a block in the cache to be writtenin SLC mode), the processing device can determine to write the garbagecollection data of the third data block 590 to the available data blockindicated by the garbage collection cursor 570.

Responsive to determining to write the garbage collection data to theavailable data block indicated by the garbage collection cursor 570, thegarbage collection data of the third data block 590 can be written tothe available data block indicated by the garbage collection cursor 570.The unneeded data, and the needed, written data, of the third data block590 can be removed from the third data block 590.

FIG. 6 illustrates an example machine of a computer system 600 withinwhich a set of instructions, for causing the machine to perform any oneor more of the methodologies discussed herein, can be executed. In someembodiments, the computer system 600 can correspond to a host system(e.g., the host system 120 of FIG. 1) that includes, is coupled to, orutilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1)or can be used to perform the operations of a controller (e.g., toexecute an operating system to perform operations corresponding to thecursor component 113 of FIG. 1). In alternative embodiments, the machinecan be connected (e.g., networked) to other machines in a LAN, anintranet, an extranet, and/or the Internet. The machine can operation inthe capacity of a server or a client machine in client-server networkenvironment, as a peer machine in a peer-to-peer (or distributed)network environment, or as a server or a client machine in a cloudcomputing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box(STB), a Personal Digital Assistant (PDA), a cellular telephone, a webappliance, a server, a network router, a switch or bridge, or anymachine capable of executing a set of instructions (sequential orotherwise) that specify actions to be taken by that machine. Further,while a single machine is illustrated, the term “machine” shall also betaken to include any collection of machines that individually or jointlyexecute a set (or multiple sets) of instructions to perform any one ormore of the methodologies discussed herein.

The example computer system 600 includes a processing device 602, a mainmemory 604 (e.g., read-only memory (ROM), flash memory, dynamic randomaccess memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM(RDRAM), etc.), a static memory 606 (e.g., flash memory, static randomaccess memory (SRAM), etc.), and a data storage system 618, whichcommunicate with each other via a bus 630.

Processing device 602 represents one or more general-purpose processingdevices such as a microprocessor, a central processing unit, or thelike. More particularly, the processing device can be a complexinstruction set computing (CISC) microprocessor, reduced instruction setcomputing (RISC) microprocessor, very long instruction word (VLIW)microprocessor, or a processor implementing other instruction sets, orprocessors implementing a combination of instruction sets. Processingdevice 602 can also be one or more special-purpose processing devicessuch as an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), a digital signal processor (DSP),network processor, or the like. The processing device 602 is configuredto execute instructions 626 for performing the operations and stepsdiscussed herein. The computer system 600 can further include a networkinterface drive 608 to communicate over the network 620.

The data storage system 618 can include a machine-readable storagemedium 624 (also known as a computer-readable medium) on which is storedone or more sets of instructions 626 or software embodying any one ormore of the methodologies or functions described herein. Theinstructions 626 can also reside, completely or at least partially,within the main memory 604 and/or within the processing device 602during execution thereof by the computer system 600, the main memory 604and the processing device 602 also constituting machine-readable storagemedia. The machine-readable storage medium 624, data storage system 618,and/or main memory 604 can correspond to the memory sub-system 110 ofFIG. 1.

In one embodiment, the instructions 626 include instructions toimplement functionality corresponding to a cursor component (e.g., thecursor component 113 of FIG. 1). While the machine-readable storagemedium 624 is shown in an example embodiment to be a single medium, theterm “machine-readable storage medium” should be taken to include asingle medium or multiple media that store the one or more sets ofinstructions. The term “machine-readable storage medium” shall also betaken to include any medium that is capable of storing or encoding a setof instructions for execution by the machine and that cause the machineto perform any one or more of the methodologies of the presentdisclosure. The term “machine-readable storage medium” shall accordinglybe taken to include, but not be limited to, solid-state memories,optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. These algorithmic descriptions andrepresentations are the ways used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and general,conceived to be a self-consistent sequence of operations leading to adesired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. The presentdisclosure can refer to the action and processes of a computer system,or similar electronic computing device, that manipulates and transformsdata represented as physical (electronic) quantities within the computersystem's registers and memories into other data similarly represented asphysical quantities within the computer system memories or registers orother such information storage systems.

The present disclosure also relates to an apparatus for performing theoperations herein. This apparatus can be specially constructed for theintended purposes, or it can include a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program can be stored in a computerreadable storage medium, such as, but not limited to, any type of diskincluding floppy disks, optical disks, CD-ROMs, and magnetic-opticaldisks, read-only memories (ROMs), random access memories (RAMs), EPROMs,EEPROMs, magnetic or optical cards, or any type of media suitable forstoring electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or apparatus. Various general purpose systemscan be used with programs in accordance with the teachings herein, or itcan prove convenient to construct a more specialized apparatus toperform the method. The structure for a variety of these systems willappear as set forth in the description below. In addition, the presentdisclosure is not described with reference to any particular programminglanguage. It will be appreciated that a variety of programming languagescan be used to implement the teachings of the disclosure as describedherein.

The present disclosure can be provided as a computer program product, orsoftware, that can include a machine-readable medium having storedthereon instructions, which can be used to program a computer system (orother electronic devices) to perform a process according to the presentdisclosure. A machine-readable medium includes any mechanism for storinginformation in a form readable by a machine (e.g., a computer. In someembodiments, a machine-readable (e.g., computer-readable) mediumincludes a machine (e.g., a computer) readable storage medium such as aread only memory (“ROM”), random access memory (“RAM”), magnetic diskstorage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have beendescribed with reference to specific example embodiments thereof. Itwill be evident that various modifications can be made thereto withoutdeparting from the broader spirit and scope of embodiments of thedisclosure as set forth in the following claims. The specification anddrawings are, accordingly, to be regarded in an illustrative senserather than a restrictive sense.

What is claimed is:
 1. A method comprising: programming incoming hostdata to a first set of blocks indicated by a first cursor of a memorysub-system, wherein the first set of blocks is associated with a firstwrite mode; determining that a second set of blocks associated with asecond write mode is available to store the incoming host data prior toclosing one or more of the first set of blocks; programming the incominghost data to the second set of blocks in view of a second cursor of thememory sub-system; and performing a media management operation to closethe one or more of the first set of blocks.
 2. The method of claim 1,wherein determining that the second set of blocks associated with thesecond write mode are available to store the incoming host datacomprises: detecting that the media management operation performed atone or more of the second set of blocks has completed.
 3. The method ofclaim 2, wherein the media management operation comprises a garbagecollection operation.
 4. The method of claim 1, wherein the first writemode corresponds to a first number of bits per memory cell of the memorysub-system and the second write mode corresponds to a second number ofbits per memory cell of the memory sub-system, and wherein the firstnumber of bits per memory cell is larger than the second number of bitsper memory cell.
 5. The method of claim 4, wherein the first write modecorresponds to two or more bits per memory cell of the memory sub-systemand the second write mode corresponds to one bit per memory cell of thememory sub-system.
 6. The method of claim 1, wherein the second set ofblocks is associated with a cache of the memory sub-system.
 7. Themethod of claim 1, wherein the first cursor and the second cursor eachindicate one or more blocks of the memory sub-system for which to writedata.
 8. The method of claim 1, wherein the second cursor is a garbagecollection cursor.
 9. A system comprising: a memory device; and aprocessing device, operatively coupled with the memory device,configured to perform operations comprising: programming incoming hostdata to a first set of blocks indicated by a first cursor of a memorysub-system, wherein the first set of blocks is associated with a firstwrite mode; determining that a second set of blocks associated with asecond write mode is available to store the incoming host data prior toclosing one or more of the first set of blocks; programming the incominghost data to the second set of blocks in view of a second cursor of thememory sub-system; and performing a media management operation to closethe one or more of the first set of blocks.
 10. The system of claim 9,wherein determining that the second set of blocks associated with thesecond write mode are available to store the incoming host datacomprises: detecting that the media management operation performed atone or more of the second set of blocks has completed.
 11. The system ofclaim 10, wherein the media management operation comprises a garbagecollection operation.
 12. The system of claim 9, wherein the first writemode corresponds to a first number of bits per memory cell of the memorysub-system and the second write mode corresponds to a second number ofbits per memory cell of the memory sub-system, and wherein the firstnumber of bits per memory cell is larger than the second number of bitsper memory cell.
 13. The system of claim 12, wherein the first writemode corresponds to two or more bits per memory cell of the memorysub-system and the second write mode corresponds to one bit per memorycell of the memory sub-system.
 14. The system of claim 9, wherein thesecond set of blocks is associated with a cache of the memorysub-system.
 15. A tangible, non-transitory computer-readable mediumstoring instructions that, when executed, cause a processing device toperform operations comprising: programming incoming host data to a firstset of blocks indicated by a first cursor of a memory sub-system,wherein the first set of blocks is associated with a first write mode;determining that a second set of blocks associated with a second writemode is available to store the incoming host data prior to closing oneor more of the first set of blocks; programming the incoming host datato the second set of blocks in view of a second cursor of the memorysub-system; and performing a media management operation to close the oneor more of the first set of blocks.
 16. The non-transitorycomputer-readable medium of claim 15, wherein determining that thesecond set of blocks associated with the second write mode are availableto store the incoming host data comprises: detecting that the mediamanagement operation performed at one or more of the second set ofblocks has completed.
 17. The non-transitory computer-readable medium ofclaim 16, wherein the media management operation comprises a garbagecollection operation.
 18. The non-transitory computer-readable medium ofclaim 15, wherein the first write mode corresponds to a first number ofbits per memory cell of the memory sub-system and the second write modecorresponds to a second number of bits per memory cell of the memorysub-system, and wherein the first number of bits per memory cell islarger than the second number of bits per memory cell.
 19. Thenon-transitory computer-readable medium of claim 18, wherein the firstwrite mode corresponds to two or more bits per memory cell of the memorysub-system and the second write mode corresponds to one bit per memorycell of the memory sub-system.
 20. The non-transitory computer-readablemedium of claim 15, wherein the second set of blocks is associated witha cache of the memory sub-system.